In general, memory devices or systems can be segmented in 3 distinct categories: internet-of-things (IoT) memories, embedded memories, and high-density high-volume memories. The memory requirements (cost, density, speed, endurance, retention, power consumption) are quite different for each of these 3 categories.
IoT memories tend to be inexpensive, power-efficient, and low-density. Memories embedded in complex system chips tend to be fast, area-efficient, and medium-density. High-density high-volume memories must be scalable to small geometries to be cost effective.
The high-density high-volume memory category is currently dominated by DRAM (which is volatile) and NAND Flash (which is non-volatile).
DRAM is very-fast, exhibits exceptional endurance, and is therefore best suited for fast system memory. DRAM, however, is expensive and volatile (for example, the data may need to be refreshed every 60 milliseconds) and sacrifices retention to maximize speed and endurance.
In sharp contrast, NAND Flash is inexpensive with much higher bit capacity and good retention, and is best suited for low-cost silicon storage. NAND Flash, however, sacrifices both speed and endurance to maximize retention.
Being limited to two dimensions (2D), DRAM will likely remain expensive since silicon area largely defines cost per gigabyte. In contrast, the cost of NAND Flash is expected to decline over time because of three dimensional (3D) stacking. The cost gap between DRAM and NAND Flash will likely increase over time.
DRAM and NAND Flash fit their sweet spots near perfectly and it seems highly unlikely that a universal memory combining the best of DRAM and NAND Flash will ever exist. It is equally unlikely that any emerging memory technology will replace DRAM because its speed and endurance combination is exceptionally hard to beat. Furthermore, there is no economic justification to build a NAND Flash replacement for high-density applications while NAND Flash prices continue to decrease.
However, as data processing and storage needs continue their rapid increase for mobile devices and cloud data centers, the industry needs a new non-volatile memory with attributes much closer to DRAM (because it is impossible to replace) than to NAND Flash (because it does not need to be replaced).
This vast space between DRAM and NAND Flash is therefore an opportunity for innovation.
Storage Class Memory is an emerging non-volatile memory segment positioned between the most successful system memory (DRAM) and the most successful silicon storage (NAND Flash). There are many opportunities for new memories in the vast space between DRAM and NAND Flash, each with different speed, endurance and retention metrics.
The biggest opportunities are always where the difficulty is greatest and that is in the space closest to DRAM. The ultimate market demand is therefore for Storage Class Memory with DRAM speed, the highest endurance achievable with this speed, a cost per gigabyte closer to NAND Flash, and a pragmatic retention far superior to DRAM retention.
Furthermore, certain semiconductor memory technologies have applied a principal of geometric redundancy, where multiple data bits may be stored in a single cell. This property of a memory cell to support a multiple of values is sometimes referred to as its dynamic range. To date the for memory cells have abilities to support a dynamic range anywhere between 1 and 4 bits. These combined properties of semiconductors have increased capacities and reduced costs.
Another issue associated with semiconductor memory manufacturing has been the substantial costs of the semiconductor foundries which can be more than a billion dollars to establish. Amortizing expenses increase the cost of memory chips. Now, with advances in foundry resolutions enabling smaller cell sizes and the geometric redundancy of multiple bit-level per memory cell semiconductor memory is actually cheaper per unit cost, and substantially more rugged in terms of high G forces than memory files on a disk drive.
In Flash memories, there have been improvements, but they have become susceptible to write cycle limitations and ability to support dynamic ranges are diminished as the quantum limit is approached. Another issue with Flash memory is its limitations in write speeds and the number of write cycle limitations the cell will tolerate before it permanently fails.
Accordingly, what is desired is a memory system and method which overcomes the above-identified problems. The systems and methods should be easily implemented, cost effective, and adaptable to existing storage applications.